1. Field of the Invention
The present invention relates to integrators with a sampling stage, and in particular, to such integrators employing a switched capacitor in the sampling stage.
2. Description of the Prior Art
Integrators which periodically sample an input signal which is to be integrated which make use of a switch capacitor in the sampling stage are known from IEEE Journal of Solid-State Circuits, Vol. SC-12, No. 6, December, 1977, at pages 600-608, particularly FIG. 2(b). In such devices, within each sampling period a portion of the noise voltages generated in the amplifier stages is supplied to the capacitance which is disposed in the feedback path. The periodically supplied noise voltage components accumulate and thus considerably falsify the integration result. In embodiments utilizing a number of amplifier stages, the integration error resulting from the noise voltages associated with the first amplifier stage contributes the greatest amount to the overall error, for the reason that those noise voltages are subjected to the greatest amplification. It is a problem of devices such as those described above to reduce the influence of the noise voltages generated in the amplifier stages on the integration result.